The present invention relates to a method for manufacturing a semiconductor device in which the element isolation technique is improved.
A semiconductor device, especially, a complementary MOS transistor (CMOS transistor) has a structure in which an n-channel MOS transistor is formed in the surface layer of a p-type island well region of an n-type semiconductor substrate, and a p-channel MOS transistor is formed in part of a substrate surface excluding the p-type well region. The semiconductor integrated circuit including such a CMOS transistor has electrical characteristics, such as power consumption, that are better than those of a semiconductor integrated circuit which includes MOS transistors of a single channel.
Conventional CMOS integrated circuit (CMOS-IC) and a conventional CMOS large scale integration (CMOS-LSI) have structures in which n- and p-channel MOS transistors are isolated by a dielectric material, as shown in FIG. 1. The CMOS-IC and CMOS-LSI are manufactured by the following method.
After a p-type well region 2 is selectively formed in an n-type semiconductor substrate 1, a field oxide film 3 is selectively formed by the Locos method to isolate elements. Gate electrodes 5.sub.1 and 5.sub.2 of impurity-doped polycrystalline silicon are formed on gate oxide films 4.sub.1 and 4.sub.2 on island surface regions of the semiconductor substrate 1 and the p-type well region 2 which are isolated by the field oxide film 3. Subsequently, a p-type impurity is diffused in the island region of the semiconductor substrate 1 using a photoresist pattern (not shown) and the gate electrode 5.sub.1 as a mask to form p.sup.+ -type regions 6 which function as the source and the drain. An n-type impurity is then diffused using a photoresist pattern (not shown) and the gate electrode 5.sub.2 and a mask to form n.sup.+ -type regions 7 which function as the source and the drain. A CVD-SiO.sub.2 film 8 is formed to cover the entire surface and contact holes 9 are formed in the CVD-SiO.sub.2 film 8. Aluminum electrodes 10 are then deposited in the contact holes 9 so as to contact the p.sup.+ -type regions 6 and the n.sup.+ -type regions 7. Thus, a CMOS-IC or CMOS-LSI is prepared.
In the CMOS-IC shown in FIG. 1, the Locos method for forming the field oxide film as the element isolation region results in great patterning error, so that it cannot be applied to prepare a highly integrated semiconductor device. Although the CMOS requires only a small power consumption, since the p-type well region 2 is formed in the n-type semiconductor substrate 1, a parasitic pnp transistor is formed which has the p.sup.+ -type regions 6 of the p-channel MOS transistor as the emitter, the n-type semiconductor substrate 1 as the base, and the p-type well region 2 as the collector, and at the same time, a parasitic npn transistor is formed which has the n.sup.+ -type regions 7 of the n-channel MOS transistor as the emitter, the p-type well region 2 as the base, and the n-type semiconductor substrate as the collector. A thyristor constituted by the parasitic transistors causes the latch-up phenomenon. In the CMOS-IC shown in FIG. 1, the field oxide film 3 which has a width of more than about 12 .mu.m is formed in a portion indicated by a length L between the p.sup.+ -type region 6 and the n.sup.+ -type region 7 adjacent thereto. In the CMOS-IC and the like, the element micronization and hence the high packing density of the device are limited if the latch-up phenomenon is to be prevented.